So the greatest offset relative to $s will be 2^15. But, now if the 'offset' is 16-bit signed then automatically we know it can take the range of -(2^15) -> (2^15)-1 and because it will be relative distance from $s, we can take the larger of the magnitudes. of the MIPS instruction set is the value of the offset. In this case, we don't shift by 2 because there are operations that load/store other things besides words, such as LH, LB or SH and SB. The three examples show that the jump distance of the branch instruction is. For LW, we know the address is calculated as Addr=R+SE(offset), also defined on the MIPS Green Sheet. However, the two bits are always 00 and cannot be changed so the max branch distance you can achieve is PC+(2^17-4).įor the second question, it is asking for the maximum distance from $s. And because we shift left by 2 (multiply by 4 to word-align), we actually have 2 extra bits to play with. Now obviously, we can rationalize that we must AT LEAST be able to branch to location 2^15 (Because of Sign-Extending) relative to our current PC, but the question is asking for the maximum branch distance that can be achieved. But the important thing to note is how PC will be updated: PC=PC+SE(IR::00) as defined on the MIPS Green Sheet. The correct answer to you're question should be as follows:įor the first question, we know BEQ uses PC-Relative addressing which is hopefully self-explanatory. Hence, an instruction passes through a stage even if there is nothing to do, because later instructions are already progress- ing at the maximum rate.You're question appears to be asking for ranges, but the answer given are for the number possible branch locations. There may be MIPS assemblers which allow you to use immediate. But whereas the immediate field in the ADDI instruction is used for storing the immediate operand for the addition, it's used for storing the branch offset in the case of BEQ/BNE. Since every instruction behind the store is already in progress, we have no way to accelerate those instructions. The reason is the instruction encoding: Both ADDI and BNE/BEQ are I-Type instructions. For this instruction, nothing happens in the write-back stage. Write-back: The bottom portion of Figure 4.40 shows the final step of the store. The only way to make the data available during the MEM stage is to place the data into the EX/MEM pipe line register in the EX stage, just as we stored the effective address into EX/MEM.ĥ. Note that the register containing the data to be stored was read in an earlier stage and stored in ID/EX. Memory access: The top portion ofFigure 4.40 shows the data being written to memory. Execute and address calculation: Figure 4.39 shows the third step the effective address is placed in the EX/MEM pipeline register.Ĥ. These first two stages are executed by all instructions, since it is too early to know the type of the instruction.ģ. The bottom portion of Figure 4.36 for load instructions also shows the operations of the second stage for stores. ![]() These three 32-bit values are all stored in the ID/EX pipeline register. ![]() Instruction decode and register file read: The instruction in the IF/ID pipe line register supplies the register numbers for reading two registers and extends the sign of the 16-bit immediate. This stage occurs before the instruction is identified, so the top portion of Figure 4.36 works for store as well as load.Ģ. Instruction fetch: The instruction is read from memory using the address in the PC and then is placed in the IF/ID pipeline register.
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